Field-Programmable Gate Array Implementation on Ethernet MAC for High Speed Secure Data Communication

  • Muhammad Latif Department of Computer Science, Bahria University Islamabad
  • Muhammad Saidu Aliero School of IT Monash University Malaysia
Keywords: Field Programmable Gate Array, Register Transfer Level, Hardware Description Language, Media Access Controller, Unshielded Twisted Pair


Abstract: Due to increasing network connectivity, low bandwidth, high power consumption, high cost, low performance, and information security are major issues in existing networks. To provide the high-speed connectivity and data security, FPGA (Field Programmable Gate Array) based solution plays an important role over a large network. This paper introduces the FPGA based implementation of Ethernet 1000BASE-X PCS/PMA and Tri-Mode Ethernet MAC cores for gigabit Ethernet communication at low cost, low power consumption and high performance over fiber optics as well as a copper medium. The implementation of RTL (Register Transfer Level) model is achieved to develop and integrate the mentioned cores using Verilog HDL (Hardware Description Language). The Verilog HDL code is simulated for customized Xilinx Spartan 3E FPGA Board using Xilinx ISE 14.7 Design Suite.